1. Technical Field
The present application relates to semiconductor technology, and more particularly to Junction Field Effect Transistor (JFET) devices and methods of making JFET devices.
2. Related Art
JFET devices are known to have a configuration as shown in FIG. 1. The JEFT device 100 shown in FIG. 1 is formed on a semiconductor substrate 102, such as a silicon wafer. The substrate 102 may be modified by implantation processes, such as diffusion doping, ion implantation, or in-situ doping, to introduce P-type impurities. An N-well 104 is formed in the substrate 102 to provide a channel for electric charge to flows between a source and a drain terminal. The N-well 104 can be formed by known well implantation processes that introduce N-type impurities. The JFET device 100 also includes first implant regions 106 and second implant regions 108. The first implant regions 106 each include a heavier concentration of N-type impurities and can serve as a source or a drain. The implant regions 108 each include P-type impurities and can serve as a gate.
In operation, a positive drain-source voltage, VDS, induces electric charge to flow within the N-well 104 from the sources to the drain. The conductance of the N-well 104 may be controlled by a negative gate-source voltage, VGS, which induces a depletion region around each pn junction. The VGS may be varied to a point where the depletion regions pinch off the channel for electric charge flow, thereby turning off the JFET device 100. The voltage to achieve a pinch off may be designated as Vp. When a JFET device 100 is integrated into an integrated circuit, the effect of noise from the semiconductor substrate can cause Vp to vary, which results in irregularities and defects in the JFET devices. As such, isolated JFET devices are desired to allow for more precise Vp.